VLSI Design

7.

Timing and Power Analysis

7.1.

Static Timing Analysis

7.1.1.

Timing Graph Construction

7.1.2.

7.1.2.1.

7.1.2.2.

7.1.2.3.

Asynchronous Paths

7.1.3.

Delay Calculation

7.1.3.1.

7.1.3.2.

7.1.3.3.

Interconnect Delay Models

7.1.4.

Setup Time Analysis

7.1.4.1.

Setup Violations

7.1.4.2.

Setup Fixing Techniques

7.1.5.

Hold Time Analysis

7.1.5.1.

Hold Violations

7.1.5.2.

Hold Fixing Techniques

7.1.6.

Clock Domain Crossing

7.1.7.

Clock Skew and Jitter

7.1.7.1.

Clock Skew Sources

7.1.7.2.

7.1.8.

Process Voltage Temperature Variations

7.1.9.

On-Chip Variation

7.1.10.

Statistical Static Timing Analysis

7.1.11.

Multi-Mode Multi-Corner Analysis

7.2.

Dynamic Timing Analysis

7.2.1.

Simulation-Based Timing

7.2.2.

Critical Path Identification

7.2.3.

Timing Verification Flows

7.3.

7.3.1.

Power Dissipation Sources

7.3.1.1.

7.3.1.1.1.

Switching Power

7.3.1.1.2.

Short-Circuit Power

7.3.1.2.

7.3.1.2.1.

Subthreshold Leakage

7.3.1.2.2.

7.3.1.2.3.

Junction Leakage

7.3.2.

Power Estimation Techniques

7.3.2.1.

Activity-Based Estimation

7.3.2.2.

Probabilistic Estimation

7.3.2.3.

Simulation-Based Estimation

7.3.3.

Power Analysis Tools

7.3.4.

Power Optimization Techniques

7.3.4.1.

7.3.4.2.

7.3.4.3.

Multi-Voltage Design

7.3.4.4.

Dynamic Voltage Scaling

7.3.4.5.

Multi-Threshold CMOS

7.3.4.6.

7.3.4.7.

Voltage Islands

7.3.5.

Low-Power Design Methodologies

7.3.5.1.

Power-Aware Synthesis

7.3.5.2.

Power-Aware Place and Route

7.3.6.

Power Delivery Network Analysis

7.3.6.1.

IR Drop Analysis

7.3.6.2.

Electromigration Analysis

7.3.7.

Thermal Analysis

7.3.7.1.

Heat Generation

7.3.7.2.

Thermal Modeling

7.3.7.3.

Thermal Management

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8. Memory Design