VLSI Design

2.

Fundamentals of MOS Transistors

2.1.

Semiconductor Physics Basics

2.1.1.

Crystal Structure

2.1.2.

2.1.3.

Doping and Carrier Concentration

2.1.4.

2.2.

The Metal-Oxide-Semiconductor Structure

2.2.1.

MOS Capacitor Structure

2.2.2.

Energy Band Diagrams

2.2.2.1.

Flat Band Condition

2.2.2.2.

2.2.2.3.

2.2.2.4.

2.2.3.

Threshold Voltage Concept

2.2.4.

Oxide Charges and Interface States

2.3.

Types of MOSFETs

2.3.1.

n-channel MOSFET (NMOS)

2.3.1.1.

Structure and Operation

2.3.1.2.

Enhancement Mode

2.3.1.3.

2.3.2.

p-channel MOSFET (PMOS)

2.3.2.1.

Structure and Operation

2.3.2.2.

Enhancement Mode

2.3.2.3.

2.4.

Modes of Operation

2.4.1.

2.4.1.1.

Conditions for Cutoff

2.4.1.2.

Subthreshold Conduction

2.4.2.

Linear (Triode) Region

2.4.2.1.

Conditions for Linear Operation

2.4.2.2.

Resistance Characteristics

2.4.3.

Saturation Region

2.4.3.1.

Conditions for Saturation

2.4.3.2.

Current Saturation Mechanism

2.5.

I-V Characteristics

2.5.1.

Output Characteristics

2.5.2.

Transfer Characteristics

2.5.3.

Channel Formation and Inversion

2.5.4.

Temperature Effects

2.5.5.

Process Variations

2.6.

The MOS Transistor as a Switch

2.6.1.

On-State and Off-State Behavior

2.6.2.

Switching Speed

2.6.3.

Applications in Logic Circuits

2.7.

Second-Order Effects

2.7.1.

Channel-Length Modulation

2.7.2.

Body Effect (Substrate Bias Effect)

2.7.3.

Velocity Saturation

2.7.4.

Mobility Degradation

2.7.5.

Hot Carrier Effects

2.7.6.

Short-Channel Effects

2.7.6.1.

Drain-Induced Barrier Lowering (DIBL)

2.7.6.2.

Threshold Voltage Roll-Off

2.7.6.3.

2.7.7.

Narrow-Width Effects

2.7.8.

Gate-Induced Drain Leakage (GIDL)

2.8.

MOS Device Capacitances

2.8.1.

Gate Capacitance

2.8.1.1.

Overlap Capacitance

2.8.1.2.

Intrinsic Capacitance

2.8.1.3.

Fringing Capacitance

2.8.2.

Junction Capacitance

2.8.2.1.

Source/Drain to Substrate Capacitance

2.8.2.2.

Voltage Dependence

2.9.

CMOS Technology

2.9.1.

CMOS Process Overview

2.9.2.

The n-well Process

2.9.3.

The p-well Process

2.9.4.

Twin-tub Process

2.9.5.

Silicon-on-Insulator (SOI)

2.9.6.

CMOS Fabrication Steps

2.9.6.1.

Substrate Preparation

2.9.6.2.

2.9.6.3.

Gate Oxide Growth

2.9.6.4.

Polysilicon Deposition

2.9.6.5.

Source/Drain Formation

2.9.6.6.

2.9.7.

Advantages of CMOS Technology

2.9.8.

CMOS Scaling Challenges

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3. CMOS Logic and Circuit Design