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Engineering
Computer Engineering
VLSI Design
1. Introduction to VLSI
2. Fundamentals of MOS Transistors
3. CMOS Logic and Circuit Design
4. The VLSI Design Process
5. Physical Design
6. Verification and Testing
7. Timing and Power Analysis
8. Memory Design
9. System-on-Chip Design
10. Signal Integrity and Interconnect
11. Advanced VLSI Topics
Physical Design
Introduction to Physical Layout
Layout Abstraction Levels
Layout Representation Formats
GDSII Format
OASIS Format
LEF/DEF Formats
Design Database Management
Design Rules and Layout
Lambda-based Design Rules
Concept and Application
Scalability Benefits
Micron-based Design Rules
Absolute Dimensions
Technology Nodes
Scaling Challenges
Design Rule Categories
Width Rules
Spacing Rules
Enclosure Rules
Extension Rules
Stick Diagrams
Purpose and Construction
Layout Planning
Floorplanning
Floorplan Objectives
Block Placement and Shaping
Aspect Ratio Considerations
Block Orientation
Power and Ground Planning
Power Grid Design
Power Ring Construction
Power Stripes
Electromigration Considerations
I/O Pad Placement
Pad Ring Design
Signal Integrity Considerations
Floorplan Optimization
Area Minimization
Wirelength Estimation
Hierarchical Floorplanning
Placement
Placement Objectives
Standard Cell Placement
Row-Based Placement
Site Alignment
Placement Algorithms
Min-Cut Placement
Simulated Annealing
Analytical Placement
Force-Directed Placement
Placement Constraints
Timing-Driven Placement
Congestion-Aware Placement
Global and Detailed Placement
Placement Optimization
Clock Tree Synthesis
Clock Distribution Networks
Clock Tree Topologies
H-Tree Structure
Mesh Networks
Clock Skew Minimization
Skew Sources
Balancing Techniques
Clock Latency Minimization
Clock Buffering
Buffer Insertion
Buffer Sizing
Clock Gating Integration
Useful Skew Techniques
Routing
Routing Problem Formulation
Global Routing
Routing Resource Estimation
Congestion Analysis
Layer Assignment
Detailed Routing
Track Assignment
Via Minimization
Design Rule Compliance
Routing Algorithms
Maze Routing
Line Search Algorithms
Channel Routing
Switchbox Routing
Multi-Layer Routing
Special Net Routing
Power and Ground Routing
Clock Routing
Parasitic Extraction
Resistance Extraction
Sheet Resistance
Via Resistance
Capacitance Extraction
Plate Capacitance
Fringing Capacitance
Coupling Capacitance
Inductance Extraction
Self Inductance
Mutual Inductance
Parasitic Modeling
RC Networks
RLC Networks
Impact on Performance
Delay Calculation
Power Analysis
Timing Closure
Timing Analysis in Layout
Static Timing Analysis Integration
Iterative Optimization
Placement Optimization
Routing Optimization
Buffer Insertion
Engineering Change Orders
Metal-Only ECOs
Standard Cell ECOs
Physical Verification Integration
DRC-Clean Layout
LVS-Clean Layout
Antenna Rule Compliance
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4. The VLSI Design Process
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6. Verification and Testing