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Computer Science
Computer Science Fundamentals
Computer Organization and Architecture
1. Introduction to Computer Systems
2. Data Representation
3. Instruction Set Architecture (ISA)
4. Central Processing Unit (CPU)
5. The Memory System
6. Input/Output (I/O) Organization
7. Storage Systems
8. Parallel Processing and Advanced Architectures
The Memory System
Memory Hierarchy Fundamentals
Memory Hierarchy Levels
CPU Registers
Cache Memory
L1 Cache
L2 Cache
L3 Cache
Main Memory (RAM)
Secondary Storage
Hard Disk Drives
Solid State Drives
Tertiary Storage
Optical Storage
Tape Storage
Principle of Locality
Temporal Locality
Recently Accessed Data
Loop Behavior
Spatial Locality
Sequential Access Patterns
Array Processing
Memory System Characteristics
Location Hierarchy
Capacity Scaling
Unit of Transfer
Access Methods
Sequential Access
Direct Access
Random Access
Associative Access
Performance Metrics
Access Time
Memory Cycle Time
Transfer Rate
Bandwidth
Physical Characteristics
Volatile vs Non-Volatile
Erasable vs Non-Erasable
Cost Considerations
Cost per Bit
Total System Cost
Cache Memory Systems
Cache Memory Principles
Cache Operation Fundamentals
Locality of Reference Exploitation
Cache Hit and Miss Concepts
Cache Organization
Cache Size Considerations
Block Size (Cache Line Size)
Cache Associativity
Cache Mapping Functions
Direct Mapping
Address Mapping Process
Tag Field
Index Field
Block Offset Field
Advantages and Disadvantages
Fully Associative Mapping
Tag Comparison Process
Content Addressable Memory
Advantages and Disadvantages
Set-Associative Mapping
Two-Way Set Associative
Four-Way Set Associative
N-Way Set Associative
Set Selection Process
Advantages and Disadvantages
Cache Replacement Policies
Least Recently Used (LRU)
Implementation Methods
Hardware Requirements
First-In First-Out (FIFO)
Implementation Simplicity
Performance Characteristics
Least Frequently Used (LFU)
Random Replacement
Hardware Simplicity
Average Performance
Cache Write Policies
Write-Hit Policies
Write-Through
Memory Consistency
Write Buffer Usage
Write-Back (Copy-Back)
Dirty Bit Management
Write-Back Buffer
Write-Miss Policies
Write-Allocate
No-Write-Allocate
Cache Performance Analysis
Hit Rate Calculation
Miss Rate Calculation
Miss Penalty Components
Average Memory Access Time (AMAT)
Cache Performance Optimization
Multi-Level Cache Systems
Inclusive Cache Hierarchy
Exclusive Cache Hierarchy
L1 Cache Characteristics
L2 Cache Characteristics
L3 Cache Characteristics
Main Memory Systems
Dynamic RAM (DRAM) Technology
DRAM Cell Structure
DRAM Operation Principles
Read Operation
Write Operation
Refresh Operation
DRAM Types
Fast Page Mode (FPM) DRAM
Extended Data Out (EDO) DRAM
Synchronous DRAM (SDRAM)
Double Data Rate SDRAM
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
DDR4 SDRAM
DDR5 SDRAM
Static RAM (SRAM) Technology
SRAM Cell Structure
SRAM vs DRAM Comparison
SRAM Applications
Memory Organization Techniques
Memory Interleaving
High-Order Interleaving
Low-Order Interleaving
Performance Benefits
Memory Banking
Error Detection and Correction
Parity Checking
Error Correcting Codes (ECC)
Single Error Correction Double Error Detection (SECDED)
Virtual Memory Systems
Virtual Memory Concepts
Address Space Separation
Memory Protection
Memory Sharing
Program Relocation
Virtual Memory Benefits
Larger Address Space
Memory Protection
Memory Sharing Between Processes
Simplified Memory Management
Paging Systems
Page and Frame Concepts
Page Size Considerations
Page Table Structure
Single-Level Page Tables
Multi-Level Page Tables
Two-Level Page Tables
Three-Level Page Tables
Inverted Page Tables
Address Translation Process
Virtual Address Components
Physical Address Generation
Page Replacement Algorithms
Optimal Algorithm (OPT)
First-In First-Out (FIFO)
Least Recently Used (LRU)
LRU Approximation Algorithms
Clock Algorithm
Second Chance Algorithm
Working Set Algorithm
Segmentation Systems
Segment Concepts
Segment Table Structure
Segmentation vs Paging
Combined Segmentation and Paging
Translation Lookaside Buffer (TLB)
TLB Structure and Operation
TLB Hit and Miss Handling
TLB Replacement Policies
TLB Performance Impact
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6. Input/Output (I/O) Organization