Computer Organization and Architecture

  1. Central Processing Unit (CPU)
    1. CPU Organization and Structure
      1. CPU Major Components
        1. Control Unit (CU)
          1. Arithmetic Logic Unit (ALU)
            1. Register Set
              1. Internal Interconnections
              2. CPU-Memory Interface
                1. CPU-I/O Interface
                2. The Instruction Execution Cycle
                  1. Fetch Phase
                    1. Instruction Address Generation
                      1. Memory Access for Instruction
                        1. Instruction Loading
                        2. Decode Phase
                          1. Instruction Parsing
                            1. Opcode Interpretation
                              1. Operand Identification
                              2. Execute Phase
                                1. ALU Operations
                                  1. Memory Access for Data
                                    1. Result Generation
                                    2. Writeback Phase
                                      1. Result Storage
                                        1. Register Updates
                                        2. Interrupt Handling
                                          1. Interrupt Recognition
                                            1. Context Switching
                                          2. CPU Registers
                                            1. User-Visible Registers
                                              1. General-Purpose Registers
                                                1. Data Storage
                                                  1. Address Storage
                                                  2. Data Registers
                                                    1. Accumulator
                                                      1. Index Registers
                                                      2. Address Registers
                                                        1. Base Registers
                                                          1. Index Registers
                                                            1. Stack Pointer
                                                            2. Condition Code Registers
                                                              1. Status Flags
                                                                1. Arithmetic Flags
                                                              2. Control and Status Registers
                                                                1. Program Counter (PC)
                                                                  1. Instruction Sequencing
                                                                    1. Branch Target Storage
                                                                    2. Instruction Register (IR)
                                                                      1. Current Instruction Storage
                                                                      2. Memory Address Register (MAR)
                                                                        1. Memory Buffer Register (MBR)
                                                                          1. Status Register
                                                                            1. Processor State Information
                                                                              1. Interrupt Masks
                                                                          2. The Datapath
                                                                            1. Datapath Components
                                                                              1. Arithmetic Logic Unit (ALU)
                                                                                1. Arithmetic Operations
                                                                                  1. Logic Operations
                                                                                    1. Comparison Operations
                                                                                      1. ALU Control Signals
                                                                                      2. Register File
                                                                                        1. Register Organization
                                                                                          1. Read/Write Ports
                                                                                            1. Register Addressing
                                                                                            2. Multiplexers
                                                                                              1. Data Selection
                                                                                                1. Control Signal Routing
                                                                                                2. Internal Buses
                                                                                                  1. Data Bus
                                                                                                    1. Address Bus
                                                                                                      1. Control Bus
                                                                                                    2. Datapath Control
                                                                                                      1. Control Signal Generation
                                                                                                        1. Timing and Synchronization
                                                                                                      2. The Control Unit
                                                                                                        1. Control Unit Functions
                                                                                                          1. Instruction Sequencing
                                                                                                            1. Control Signal Generation
                                                                                                              1. Exception Handling
                                                                                                              2. Hardwired Control Implementation
                                                                                                                1. Combinational Logic Design
                                                                                                                  1. Control Signal Timing
                                                                                                                    1. Advantages and Disadvantages
                                                                                                                    2. Microprogrammed Control
                                                                                                                      1. Microinstruction Concepts
                                                                                                                        1. Microinstruction Format
                                                                                                                          1. Horizontal Microcode
                                                                                                                            1. Vertical Microcode
                                                                                                                            2. Control Memory Organization
                                                                                                                              1. Microprogram Storage
                                                                                                                                1. Microprogram Counter
                                                                                                                                2. Microinstruction Sequencing
                                                                                                                                  1. Advantages and Disadvantages
                                                                                                                                3. CPU Performance Enhancement
                                                                                                                                  1. Instruction Pipelining
                                                                                                                                    1. Pipeline Concepts
                                                                                                                                      1. Instruction Overlap
                                                                                                                                        1. Pipeline Stages
                                                                                                                                          1. Pipeline Throughput
                                                                                                                                          2. Basic Pipeline Stages
                                                                                                                                            1. Instruction Fetch (IF)
                                                                                                                                              1. Instruction Decode (ID)
                                                                                                                                                1. Execute (EX)
                                                                                                                                                  1. Memory Access (MEM)
                                                                                                                                                    1. Write Back (WB)
                                                                                                                                                    2. Pipeline Performance
                                                                                                                                                      1. Ideal Pipeline Performance
                                                                                                                                                        1. Pipeline Efficiency
                                                                                                                                                        2. Pipeline Hazards
                                                                                                                                                          1. Structural Hazards
                                                                                                                                                            1. Resource Conflicts
                                                                                                                                                              1. Hardware Duplication
                                                                                                                                                              2. Data Hazards
                                                                                                                                                                1. Read After Write (RAW)
                                                                                                                                                                  1. Write After Read (WAR)
                                                                                                                                                                    1. Write After Write (WAW)
                                                                                                                                                                    2. Control Hazards
                                                                                                                                                                      1. Branch Instructions
                                                                                                                                                                        1. Jump Instructions
                                                                                                                                                                      2. Hazard Resolution Techniques
                                                                                                                                                                        1. Pipeline Stalling
                                                                                                                                                                          1. Bubble Insertion
                                                                                                                                                                            1. Performance Impact
                                                                                                                                                                            2. Data Forwarding
                                                                                                                                                                              1. Bypass Paths
                                                                                                                                                                                1. Forwarding Logic
                                                                                                                                                                                2. Branch Prediction
                                                                                                                                                                                  1. Static Branch Prediction
                                                                                                                                                                                    1. Dynamic Branch Prediction
                                                                                                                                                                                      1. Branch History Table
                                                                                                                                                                                        1. Two-Level Adaptive Prediction
                                                                                                                                                                                        2. Branch Target Buffer
                                                                                                                                                                                        3. Speculative Execution
                                                                                                                                                                                          1. Pipeline Flushing
                                                                                                                                                                                        4. Superscalar Architecture
                                                                                                                                                                                          1. Multiple Issue Processors
                                                                                                                                                                                            1. Instruction-Level Parallelism
                                                                                                                                                                                              1. Out-of-Order Execution
                                                                                                                                                                                                1. Register Renaming

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                                                                                                                                                                                            3. Instruction Set Architecture (ISA)

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                                                                                                                                                                                            5. The Memory System