Digital Logic Design

  1. Introduction to Hardware Description Languages
    1. Concept of HDLs
      1. Purpose and Advantages
        1. Levels of Abstraction
          1. Behavioral Level
            1. Register Transfer Level
              1. Gate Level
                1. Switch Level
                2. Simulation vs Synthesis
                  1. Design Flow with HDLs
                  2. Verilog HDL
                    1. Basic Concepts and Syntax
                      1. Lexical Elements
                        1. Data Types
                          1. Nets
                            1. Registers
                              1. Parameters
                              2. Operators
                                1. Arithmetic Operators
                                  1. Logical Operators
                                    1. Relational Operators
                                      1. Bitwise Operators
                                    2. Modules and Hierarchy
                                      1. Module Definition
                                        1. Port Declaration
                                          1. Input Ports
                                            1. Output Ports
                                              1. Inout Ports
                                              2. Module Instantiation
                                                1. Hierarchical Design
                                                2. Gate-Level Modeling
                                                  1. Primitive Gates
                                                    1. User-Defined Primitives
                                                      1. Structural Descriptions
                                                        1. Delay Modeling
                                                        2. Dataflow Modeling
                                                          1. Continuous Assignments
                                                            1. Operators and Expressions
                                                              1. Conditional Operators
                                                              2. Behavioral Modeling
                                                                1. Procedural Blocks
                                                                  1. Initial Blocks
                                                                    1. Always Blocks
                                                                      1. Control Statements
                                                                        1. If-Else Statements
                                                                          1. Case Statements
                                                                            1. Loop Statements
                                                                          2. Tasks and Functions
                                                                            1. Task Definition and Calling
                                                                              1. Function Definition and Calling
                                                                                1. Differences between Tasks and Functions
                                                                              2. VHDL
                                                                                1. Basic Concepts and Syntax
                                                                                  1. Design Units
                                                                                    1. Data Types
                                                                                      1. Scalar Types
                                                                                        1. Composite Types
                                                                                          1. Access Types
                                                                                          2. Operators
                                                                                            1. Logical Operators
                                                                                              1. Arithmetic Operators
                                                                                                1. Relational Operators
                                                                                              2. Entity and Architecture
                                                                                                1. Entity Declaration
                                                                                                  1. Port Declaration
                                                                                                    1. Generic Declaration
                                                                                                    2. Architecture Body
                                                                                                      1. Architecture Styles
                                                                                                    3. Dataflow Modeling
                                                                                                      1. Concurrent Signal Assignment
                                                                                                        1. Conditional Signal Assignment
                                                                                                          1. Selected Signal Assignment
                                                                                                          2. Behavioral Modeling
                                                                                                            1. Process Statements
                                                                                                              1. Sequential Statements
                                                                                                                1. Variable Assignment
                                                                                                                  1. Signal Assignment
                                                                                                                    1. Control Statements
                                                                                                                  2. Structural Modeling
                                                                                                                    1. Component Declaration
                                                                                                                      1. Component Instantiation
                                                                                                                        1. Port Mapping
                                                                                                                        2. Packages and Libraries
                                                                                                                          1. Standard Packages
                                                                                                                            1. User-Defined Packages
                                                                                                                              1. Library Usage
                                                                                                                            2. Simulation and Synthesis
                                                                                                                              1. Writing Testbenches
                                                                                                                                1. Stimulus Generation
                                                                                                                                  1. Clock Generation
                                                                                                                                    1. Output Monitoring
                                                                                                                                      1. File I/O Operations
                                                                                                                                      2. Simulation Process
                                                                                                                                        1. Compilation
                                                                                                                                          1. Elaboration
                                                                                                                                            1. Simulation Execution
                                                                                                                                            2. Synthesis Process
                                                                                                                                              1. RTL Synthesis
                                                                                                                                                1. Technology Mapping
                                                                                                                                                  1. Optimization
                                                                                                                                                  2. Verification Techniques
                                                                                                                                                    1. Functional Verification
                                                                                                                                                      1. Timing Verification
                                                                                                                                                        1. Formal Verification
                                                                                                                                                        2. Digital Design Flow
                                                                                                                                                          1. Design Entry
                                                                                                                                                            1. Functional Simulation
                                                                                                                                                              1. Synthesis
                                                                                                                                                                1. Post-Synthesis Simulation
                                                                                                                                                                  1. Implementation
                                                                                                                                                                    1. Post-Implementation Simulation
                                                                                                                                                                      1. Hardware Testing

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                                                                                                                                                                  8. Memory and Programmable Logic

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                                                                                                                                                                  1. Foundations of Digital Logic