Digital Logic Design

6.

Registers and Counters

6.1.

6.1.1.

Basic Register Operations

6.1.1.1.

6.1.1.2.

Clear Operation

6.1.1.3.

6.1.2.

Shift Registers

6.1.2.1.

Serial-In Serial-Out

6.1.2.1.1.

Structure and Operation

6.1.2.1.2.

Timing Diagrams

6.1.2.2.

Serial-In Parallel-Out

6.1.2.2.1.

Structure and Operation

6.1.2.3.

Parallel-In Serial-Out

6.1.2.3.1.

Structure and Operation

6.1.2.4.

Parallel-In Parallel-Out

6.1.2.4.1.

Structure and Operation

6.1.2.5.

Bidirectional Shift Register

6.1.2.5.1.

Left and Right Shift Operations

6.1.2.5.2.

6.1.3.

Universal Shift Register

6.1.3.1.

6.1.3.2.

Functionality and Applications

6.1.4.

Register Applications

6.1.4.1.

6.1.4.2.

6.1.4.3.

Serial Communication

6.2.

6.2.1.

Ripple Counters

6.2.1.1.

Binary Ripple Counter

6.2.1.1.1.

Structure and Operation

6.2.1.1.2.

Timing Analysis

6.2.1.1.3.

Propagation Delay Issues

6.2.1.2.

6.2.1.2.1.

BCD Ripple Counter

6.2.1.2.2.

Modulo-10 Operation

6.2.1.3.

Modulo-N Counters

6.2.1.3.1.

Design Techniques

6.2.1.3.2.

6.2.2.

Synchronous Counters

6.2.2.1.

Binary Up Counter

6.2.2.1.1.

Design and Operation

6.2.2.1.2.

6.2.2.2.

Binary Down Counter

6.2.2.2.1.

Design and Operation

6.2.2.3.

Up-Down Counter

6.2.2.3.1.

6.2.2.3.2.

Design Implementation

6.2.2.4.

6.2.2.4.1.

Synchronous Design

6.2.2.4.2.

6.2.2.5.

Modulo-N Synchronous Counters

6.2.2.5.1.

Design Methodology

6.2.2.5.2.

State Assignment

6.2.3.

Special Counters

6.2.3.1.

6.2.3.1.1.

Structure and Operation

6.2.3.1.2.

Johnson Counter

6.2.3.1.2.1.

Structure and Operation

6.2.3.1.2.2.

Twisted Ring Counter

6.2.3.1.2.3.

Decoding States

6.2.4.

Counter Applications

6.2.4.1.

Frequency Division

6.2.4.2.

Timing Generation

6.2.4.3.

6.2.4.4.

Address Generation

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7. Asynchronous Sequential Logic