Useful Links
Engineering
Computer Engineering
Digital Logic Design
1. Foundations of Digital Logic
2. Boolean Algebra and Logic Gates
3. Gate-Level Minimization
4. Combinational Logic
5. Synchronous Sequential Logic
6. Registers and Counters
7. Asynchronous Sequential Logic
8. Memory and Programmable Logic
9. Introduction to Hardware Description Languages
Synchronous Sequential Logic
Introduction to Sequential Circuits
Combinational vs Sequential Logic
Concept of State and Memory
Types of Sequential Circuits
Synchronous Sequential Circuits
Asynchronous Sequential Circuits
Clock Signal Characteristics
Storage Elements
Latches
SR Latch using NOR Gates
Truth Table and Operation
Timing Characteristics
SR Latch using NAND Gates
Truth Table and Operation
Timing Characteristics
D Latch
Truth Table and Operation
Enable Input
Transparency Problem
Flip-Flops
Clock Signal and Edge-Triggering
Positive Edge Triggering
Negative Edge Triggering
Clock Transition
SR Flip-Flop
Truth Table and Operation
Characteristic Equation
D Flip-Flop
Truth Table and Operation
Characteristic Equation
JK Flip-Flop
Truth Table and Operation
Characteristic Equation
Toggle Operation
T Flip-Flop
Truth Table and Operation
Characteristic Equation
Frequency Division
Master-Slave Configuration
Structure and Operation
Timing Considerations
Flip-Flop Conversions
D to JK Conversion
JK to D Conversion
JK to T Conversion
T to JK Conversion
Timing Parameters
Setup Time
Hold Time
Propagation Delay
Clock-to-Q Delay
Analysis of Clocked Sequential Circuits
State Equations
Next State Equations
Output Equations
State Table Construction
State Diagram Construction
Timing Diagrams
Mealy and Moore Models
Mealy Model Characteristics
Moore Model Characteristics
Comparison and Conversion
Design of Clocked Sequential Circuits
Design Procedure
Problem Specification
State Diagram Construction
State Table Derivation
State Assignment
Flip-Flop Input Equation Derivation
Output Equation Derivation
Logic Diagram Implementation
State Reduction
Equivalent States
State Minimization Techniques
Implication Table Method
State Assignment
Binary State Assignment
One-Hot State Assignment
Gray Code Assignment
Assignment Guidelines
Previous
4. Combinational Logic
Go to top
Next
6. Registers and Counters