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Engineering
Computer Engineering
Digital Logic Design
1. Foundations of Digital Logic
2. Boolean Algebra and Logic Gates
3. Gate-Level Minimization
4. Combinational Logic
5. Synchronous Sequential Logic
6. Registers and Counters
7. Asynchronous Sequential Logic
8. Memory and Programmable Logic
9. Introduction to Hardware Description Languages
3.
Gate-Level Minimization
3.1.
The Map Method
3.1.1.
Structure of Karnaugh Maps
3.1.2.
Two-Variable K-Map
3.1.2.1.
Construction
3.1.2.2.
Grouping Rules
3.1.3.
Three-Variable K-Map
3.1.3.1.
Construction
3.1.3.2.
Grouping Rules
3.1.4.
Four-Variable K-Map
3.1.4.1.
Construction
3.1.4.2.
Grouping Rules
3.1.5.
Five-Variable K-Map
3.1.5.1.
Construction
3.1.5.2.
Grouping Rules
3.1.6.
Grouping for Simplification
3.1.6.1.
Groups of Powers of Two
3.1.6.2.
Overlapping Groups
3.1.6.3.
Adjacent Cells
3.1.7.
Don't-Care Conditions
3.1.7.1.
Identification and Use
3.1.7.2.
Optimal Grouping with Don't-Cares
3.2.
SOP Simplification using K-Maps
3.2.1.
Steps for SOP Minimization
3.2.2.
Prime Implicants
3.2.3.
Essential Prime Implicants
3.2.4.
Example Problems
3.3.
POS Simplification using K-Maps
3.3.1.
Steps for POS Minimization
3.3.2.
Maxterm Grouping
3.3.3.
Example Problems
3.4.
NAND and NOR Implementation
3.4.1.
Two-Level NAND Implementation
3.4.2.
Two-Level NOR Implementation
3.4.3.
Conversion from SOP to NAND
3.4.4.
Conversion from POS to NOR
3.4.5.
Multi-Level NAND/NOR Networks
3.5.
Quine-McCluskey Method
3.5.1.
Steps in the Tabulation Method
3.5.2.
Finding Prime Implicants
3.5.3.
Prime Implicant Chart
3.5.4.
Selection of Essential Prime Implicants
3.5.5.
Petrick's Method
3.5.6.
Comparison with K-Map Method
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2. Boolean Algebra and Logic Gates
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4. Combinational Logic