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Engineering
Computer Engineering
Digital Logic Design
1. Foundations of Digital Logic
2. Boolean Algebra and Logic Gates
3. Gate-Level Minimization
4. Combinational Logic
5. Synchronous Sequential Logic
6. Registers and Counters
7. Asynchronous Sequential Logic
8. Memory and Programmable Logic
9. Introduction to Hardware Description Languages
Gate-Level Minimization
The Map Method
Structure of Karnaugh Maps
Two-Variable K-Map
Construction
Grouping Rules
Three-Variable K-Map
Construction
Grouping Rules
Four-Variable K-Map
Construction
Grouping Rules
Five-Variable K-Map
Construction
Grouping Rules
Grouping for Simplification
Groups of Powers of Two
Overlapping Groups
Adjacent Cells
Don't-Care Conditions
Identification and Use
Optimal Grouping with Don't-Cares
SOP Simplification using K-Maps
Steps for SOP Minimization
Prime Implicants
Essential Prime Implicants
Example Problems
POS Simplification using K-Maps
Steps for POS Minimization
Maxterm Grouping
Example Problems
NAND and NOR Implementation
Two-Level NAND Implementation
Two-Level NOR Implementation
Conversion from SOP to NAND
Conversion from POS to NOR
Multi-Level NAND/NOR Networks
Quine-McCluskey Method
Steps in the Tabulation Method
Finding Prime Implicants
Prime Implicant Chart
Selection of Essential Prime Implicants
Petrick's Method
Comparison with K-Map Method
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2. Boolean Algebra and Logic Gates
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4. Combinational Logic