STM32 Microcontroller Development

5.

General Purpose Input/Output (GPIO)

5.1.

GPIO Pin Configuration

5.1.1.

5.1.1.1.

5.1.1.2.

5.1.1.3.

Pull-down Input

5.1.1.4.

5.1.2.

5.1.2.1.

Push-Pull Output

5.1.2.2.

Open-Drain Output

5.1.2.3.

Output Speed Settings

5.1.3.

Alternate Function Mode

5.1.3.1.

Peripheral Pin Mapping

5.1.3.2.

Alternate Function Selection

5.1.4.

Configuration Registers

5.1.4.1.

Mode Register (MODER)

5.1.4.2.

Output Type Register (OTYPER)

5.1.4.3.

Pull-up/Pull-down Register (PUPDR)

5.2.

GPIO Operations

5.2.1.

Reading Input Pins

5.2.1.1.

Input Data Register (IDR)

5.2.1.2.

Bit-level Reading

5.2.2.

Writing Output Pins

5.2.2.1.

Output Data Register (ODR)

5.2.2.2.

Bit Set/Reset Register (BSRR)

5.2.2.3.

Atomic Operations

5.3.

Advanced GPIO Features

5.3.1.

Bit-Banding (where available)

5.3.1.1.

Bit-Banding Regions

5.3.1.2.

Atomic Bit Operations

5.3.2.

5.3.2.1.

Lock Configuration Register (LCKR)

5.3.2.2.

Pin Configuration Protection

5.4.

External Interrupts (EXTI)

5.4.1.

EXTI Line Configuration

5.4.1.1.

Line-to-Pin Mapping

5.4.1.2.

Source Selection

5.4.2.

Trigger Configuration

5.4.2.1.

Rising Edge Trigger

5.4.2.2.

Falling Edge Trigger

5.4.2.3.

Both Edges Trigger

5.4.3.

5.4.3.1.

Interrupt Mask Register (IMR)

5.4.3.2.

Event Mask Register (EMR)

5.4.3.3.

Pending Register (PR)

5.4.4.

Interrupt Service Routines

5.4.4.1.

EXTI Handler Implementation

5.4.4.2.

5.4.5.

Debouncing Techniques

5.4.5.1.

Hardware Debouncing

5.4.5.2.

Software Debouncing

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4. Core Architecture and System Control

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6. Interrupts and Exception Handling