Memory Management

5.

Non-Contiguous Memory Allocation: Segmentation

5.1.

5.1.1.

Concept of Segmentation

5.1.2.

User's View of Memory

5.1.2.1.

Logical Division of Programs

5.1.2.1.1.

5.1.2.1.2.

5.1.2.1.3.

5.1.2.1.4.

5.1.3.

Logical Address as a Two-Tuple

5.1.3.1.

5.1.3.2.

Offset within Segment

5.1.4.

Address Translation in Segmentation

5.1.4.1.

Segment Table Lookup

5.1.4.2.

Bounds Checking

5.1.4.3.

Physical Address Calculation

5.2.

5.2.1.

Purpose and Structure

5.2.2.

Segment Table Base Register (STBR)

5.2.3.

Segment Table Length Register (STLR)

5.2.4.

Structure of a Segment Table Entry

5.2.4.1.

Segment Base Address

5.2.4.2.

5.2.4.3.

Protection Bits

5.2.4.3.1.

Read Permission

5.2.4.3.2.

Write Permission

5.2.4.3.3.

Execute Permission

5.2.4.4.

Valid/Invalid Bit

5.2.4.5.

Growth Direction

5.3.

Memory Protection and Sharing in Segmentation

5.3.1.

Access Control Mechanisms

5.3.1.1.

Privilege Level Checking

5.3.1.2.

Bounds Violation Detection

5.3.2.

Sharing Segments Between Processes

5.3.2.1.

Shared Code Segments

5.3.2.2.

Shared Data Segments

5.3.2.3.

Reference Counting

5.4.

Segmentation with Paging (Combined Systems)

5.4.1.

Motivation for Combining

5.4.1.1.

Eliminating External Fragmentation

5.4.1.2.

Maintaining Logical Structure

5.4.2.

Address Translation in Combined Systems

5.4.2.1.

Two-Stage Translation Process

5.4.2.2.

Segment Table to Page Table

5.4.3.

Implementation Approaches

5.4.3.1.

Intel x86 Architecture

5.4.3.2.

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