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Computer Science
Programming
LLVM Compiler Backend
1. Introduction to Compiler Backends and LLVM
2. LLVM Intermediate Representation
3. Target Description Infrastructure
4. Instruction Selection
5. Register Allocation
6. Instruction Scheduling
7. Code Emission and Finalization
8. Advanced Backend Features
9. Backend Development
6.
Instruction Scheduling
6.1.
Scheduling Objectives
6.1.1.
Latency Minimization
6.1.2.
Throughput Maximization
6.1.3.
Resource Utilization
6.2.
Scheduling Phases
6.2.1.
Pre-Register Allocation Scheduling
6.2.1.1.
Register Pressure Reduction
6.2.1.2.
Early Optimization
6.2.2.
Post-Register Allocation Scheduling
6.2.2.1.
Final Instruction Ordering
6.2.2.2.
Anti-Dependency Handling
6.3.
Scheduling Infrastructure
6.3.1.
Scheduling Units
6.3.1.1.
SUnit Construction
6.3.1.2.
Dependency Representation
6.3.2.
Dependency Graphs
6.3.2.1.
Data Dependencies
6.3.2.2.
Control Dependencies
6.3.2.3.
Resource Dependencies
6.4.
Scheduling Algorithms
6.4.1.
List Scheduling
6.4.1.1.
Ready Queue Management
6.4.1.2.
Priority Functions
6.4.2.
Critical Path Analysis
6.4.3.
Resource Constraint Modeling
6.5.
Advanced Scheduling
6.5.1.
Software Pipelining
6.5.1.1.
Loop Kernel Scheduling
6.5.1.2.
Initiation Interval
6.5.2.
Loop Unrolling
6.5.2.1.
Unroll Factor Selection
6.5.2.2.
Schedule Impact
6.5.3.
Out-of-Order Modeling
6.5.3.1.
Hardware Constraints
6.5.3.2.
Issue Width Modeling
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5. Register Allocation
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7. Code Emission and Finalization