Useful Links
Computer Science
Programming
LLVM Compiler Backend
1. Introduction to Compiler Backends and LLVM
2. LLVM Intermediate Representation
3. Target Description Infrastructure
4. Instruction Selection
5. Register Allocation
6. Instruction Scheduling
7. Code Emission and Finalization
8. Advanced Backend Features
9. Backend Development
Instruction Scheduling
Scheduling Objectives
Latency Minimization
Throughput Maximization
Resource Utilization
Scheduling Phases
Pre-Register Allocation Scheduling
Register Pressure Reduction
Early Optimization
Post-Register Allocation Scheduling
Final Instruction Ordering
Anti-Dependency Handling
Scheduling Infrastructure
Scheduling Units
SUnit Construction
Dependency Representation
Dependency Graphs
Data Dependencies
Control Dependencies
Resource Dependencies
Scheduling Algorithms
List Scheduling
Ready Queue Management
Priority Functions
Critical Path Analysis
Resource Constraint Modeling
Advanced Scheduling
Software Pipelining
Loop Kernel Scheduling
Initiation Interval
Loop Unrolling
Unroll Factor Selection
Schedule Impact
Out-of-Order Modeling
Hardware Constraints
Issue Width Modeling
Previous
5. Register Allocation
Go to top
Next
7. Code Emission and Finalization