LLVM Compiler Backend

5.

Register Allocation

5.1.

Register Allocation Problem

5.1.1.

Virtual to Physical Mapping

5.1.2.

Resource Constraints

5.1.3.

Optimization Objectives

5.2.

Fundamental Concepts

5.2.1.

Liveness Analysis

5.2.1.1.

Live Variable Analysis

5.2.1.2.

Live Range Computation

5.2.2.

5.2.2.1.

Interval Construction

5.2.2.2.

Interval Splitting

5.2.2.3.

Interval Merging

5.2.3.

Interference Analysis

5.2.3.1.

Interference Graph

5.2.3.2.

5.3.

Allocation Strategies

5.3.1.

Spilling Mechanisms

5.3.1.1.

Spill Code Generation

5.3.1.2.

Spill Slot Assignment

5.3.1.3.

Reload Insertion

5.3.2.

Coalescing Techniques

5.3.2.1.

Move Elimination

5.3.2.2.

Register Merging

5.3.2.3.

Copy Propagation

5.3.3.

Rematerialization

5.3.3.1.

Value Recomputation

5.3.3.2.

5.4.

LLVM Register Allocators

5.4.1.

5.4.1.1.

Linear Scan Algorithm

5.4.1.2.

Performance Characteristics

5.4.2.

Greedy Allocator

5.4.2.1.

Priority-Based Selection

5.4.2.2.

Spill Cost Calculation

5.4.2.3.

Live Range Splitting

5.4.3.

5.4.3.1.

Graph-Based Formulation

5.4.3.2.

Constraint Modeling

5.5.

Post-Allocation Processing

5.5.1.

Two-Address Conversion

5.5.2.

Prologue Insertion

5.5.3.

Epilogue Insertion

5.5.4.

Stack Slot Assignment

Previous

4. Instruction Selection

Go to top

Next

6. Instruction Scheduling