UsefulLinks
Computer Science
Programming
LLVM Compiler Backend
1. Introduction to Compiler Backends and LLVM
2. LLVM Intermediate Representation
3. Target Description Infrastructure
4. Instruction Selection
5. Register Allocation
6. Instruction Scheduling
7. Code Emission and Finalization
8. Advanced Backend Features
9. Backend Development
4.
Instruction Selection
4.1.
Code Generation Pipeline
4.1.1.
Pass Sequence
4.1.2.
Pass Dependencies
4.1.3.
Pass Ordering
4.2.
SelectionDAG Framework
4.2.1.
DAG Construction
4.2.1.1.
IR to DAG Translation
4.2.1.2.
Node Creation
4.2.1.3.
Edge Formation
4.2.2.
DAG Node Types
4.2.2.1.
SDNode Properties
4.2.2.2.
Value Types
4.2.2.3.
Node Operations
4.2.3.
Machine Value Types
4.2.3.1.
Type Representation
4.2.3.2.
Type Promotion
4.2.3.3.
Type Demotion
4.2.4.
Legalization Process
4.2.4.1.
Type Legalization
4.2.4.1.1.
Type Splitting
4.2.4.1.2.
Type Widening
4.2.4.2.
Operation Legalization
4.2.4.2.1.
Operation Expansion
4.2.4.2.2.
Operation Promotion
4.2.5.
DAG Optimization
4.2.5.1.
Node Combining
4.2.5.2.
Redundancy Elimination
4.2.5.3.
Pattern Recognition
4.2.6.
Pattern Matching
4.2.6.1.
TableGen Patterns
4.2.6.2.
Custom Selection
4.2.6.3.
Pattern Priorities
4.2.7.
DAG Scheduling
4.2.7.1.
Instruction Ordering
4.2.7.2.
Dependency Analysis
4.3.
GlobalISel Framework
4.3.1.
Design Motivation
4.3.2.
MachineIR Representation
4.3.3.
GlobalISel Pipeline
4.3.3.1.
IRTranslator Pass
4.3.3.2.
Legalizer Pass
4.3.3.3.
RegisterBankSelect Pass
4.3.3.4.
InstructionSelect Pass
4.3.4.
Generic Machine Instructions
4.3.5.
Register Banks
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3. Target Description Infrastructure
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5. Register Allocation