LLVM Compiler Backend

  1. Target Description Infrastructure
    1. TargetMachine Architecture
      1. Target Configuration
        1. Triple Specification
          1. Architecture Component
            1. Vendor Component
              1. Operating System Component
                1. Environment Component
                2. Target Options
                  1. Feature Management
                  2. TableGen Description Language
                    1. TableGen Syntax
                      1. File Structure
                        1. Record Definitions
                          1. Class Hierarchies
                            1. Code Generation Backend
                            2. Target Definition Components
                              1. Processor Definitions
                                1. CPU Models
                                  1. Subtarget Features
                                    1. Scheduling Models
                                    2. Register File Description
                                      1. Register Classes
                                        1. Register Hierarchies
                                          1. Register Aliases
                                          2. Instruction Set Description
                                            1. Instruction Formats
                                              1. Encoding Specifications
                                                1. Operand Definitions
                                                2. Calling Convention Description
                                                  1. Parameter Passing Rules
                                                    1. Return Value Handling
                                                      1. Stack Management
                                                      2. Pattern Matching Rules
                                                        1. DAG Patterns
                                                          1. Instruction Selection Patterns
                                                        2. Target Implementation Classes
                                                          1. TargetLowering Class
                                                            1. Operation Legalization
                                                              1. Custom Lowering
                                                                1. Type Legalization
                                                                2. TargetInstrInfo Class
                                                                  1. Instruction Properties
                                                                    1. Scheduling Information
                                                                    2. TargetRegisterInfo Class
                                                                      1. Register Allocation Support
                                                                        1. Register Constraints
                                                                        2. TargetFrameLowering Class
                                                                          1. Stack Frame Layout
                                                                            1. Prologue Generation
                                                                              1. Epilogue Generation
                                                                              2. TargetSubtargetInfo Class
                                                                                1. Feature Management
                                                                                  1. CPU Detection

                                                                              Previous

                                                                              2. LLVM Intermediate Representation

                                                                              Go to top

                                                                              Next

                                                                              4. Instruction Selection