Useful Links
Computer Science
Software Engineering
FPGA Development
1. Introduction to FPGAs and Digital Logic
2. FPGA Architecture Fundamentals
3. Hardware Description Languages
4. The FPGA Design Flow
5. Simulation and Verification
6. Timing Constraints and Analysis
7. Advanced HDL Design Techniques
8. System-on-Chip FPGA Design
9. On-Chip Debugging and Practical Implementation
10. High-Level Synthesis
Advanced HDL Design Techniques
Finite State Machines
FSM Design Methodology
State Machine Types
Moore Machines
Output Depends on State Only
State Diagram Representation
Mealy Machines
Output Depends on State and Input
Timing Considerations
State Diagram Creation
State Definition
Transition Conditions
Output Specification
State Encoding Schemes
Binary Encoding
Minimum Bit Requirement
Sequential Assignment
Gray Encoding
Single Bit Change Between States
Reduced Switching Activity
One-Hot Encoding
Single Active Bit per State
Fast Decoding
Higher Resource Usage
Custom Encoding
Application-Specific Optimization
HDL Implementation
Single Process Implementation
Two Process Implementation
Three Process Implementation
Safe FSM Design Practices
Avoiding Illegal States
Default State Assignment
State Recovery Mechanisms
Reset Handling
FSM Optimization
State Minimization
Unused State Removal
Performance Optimization
Pipelining
Pipelining Concepts
Increasing Throughput
Latency vs. Throughput Trade-offs
Pipeline Design
Breaking Combinational Paths
Pipeline Stages and Registers
Balancing Pipeline Latency
Pipeline Depth Selection
Pipeline Hazards
Data Hazards
Control Hazards
Structural Hazards
Pipeline Control
Pipeline Enable Signals
Pipeline Flush Mechanisms
Stall Handling
Advanced Pipelining Techniques
Superpipelining
Pipeline Parallelism
Adaptive Pipelining
Clock Domain Crossing Design
Understanding Metastability
Metastable States
Resolution Time
MTBF Calculations
Synchronization Circuits
Two-Flip-Flop Synchronizers
Basic Synchronizer Design
Synchronizer Depth
Multi-Flip-Flop Synchronizers
Reset Synchronizers
Asynchronous Assert, Synchronous Deassert
Asynchronous FIFO Design
FIFO Architecture
Gray Code Counters
Binary to Gray Conversion
Gray Code Properties
Empty and Full Flag Generation
Pointer Comparison
Flag Synchronization
FIFO Depth Calculation
Handshake Protocols
Request-Acknowledge Protocols
Four-Phase Handshake
Two-Phase Handshake
Pulse Synchronizers
Edge Detection
Pulse Stretching
CDC Verification Techniques
Simulation-Based Verification
Formal Verification Methods
CDC Analysis Tools
Memory Design and Interfacing
On-Chip Memory
Inferring Block RAM in HDL
BRAM Inference Patterns
Synthesis Attributes
Single-Port RAM
Read and Write Operations
Address Decoding
Dual-Port RAM
Independent Port Operation
Collision Handling
ROM Implementation
Initialization Methods
Constant Arrays
External Memory Interfacing
SRAM Interface
Address and Data Bus
Control Signals
Timing Requirements
DRAM Interface
Row and Column Addressing
Refresh Requirements
Burst Operations
DDR SDRAM Interface
Double Data Rate Operation
DQS Strobe Signals
Calibration Requirements
Memory Controllers
Controller Architecture
Command Scheduling
Refresh Management
Error Detection and Correction
Memory Optimization Techniques
Memory Bandwidth Optimization
Latency Hiding Techniques
Cache Design Principles
Parameterized and Generic Designs
Parameterization in Verilog
Parameter Declaration
Local Parameter Usage
Parameter Override
Generate Statements with Parameters
Generics in VHDL
Generic Declaration
Generic Map
Generic Types and Constraints
Creating Reusable Modules
Configurable Interfaces
Scalable Architectures
Library Development
Configurable Design Patterns
Width Parameterization
Depth Parameterization
Feature Selection Parameters
Performance vs. Area Trade-offs
Advanced Coding Techniques
Coding for Synthesis
Synthesis-Friendly Constructs
Avoiding Non-Synthesizable Code
Resource Inference Guidelines
Code Optimization
Logic Optimization
Resource Sharing
Timing Optimization
Hierarchical Design
Module Partitioning
Interface Definition
Design Reuse Strategies
Design for Testability
Built-In Self-Test
Scan Chain Insertion
Boundary Scan
Previous
6. Timing Constraints and Analysis
Go to top
Next
8. System-on-Chip FPGA Design