FPGA Development

5.

Simulation and Verification

5.1.

The Importance of Verification

5.1.1.

Detecting Design Errors

5.1.2.

Ensuring Functional Correctness

5.1.3.

Reducing Debug Time in Hardware

5.1.4.

Cost of Late Bug Discovery

5.1.5.

Verification Methodologies

5.2.

Testbench Architecture

5.2.1.

Unit Under Test Instantiation

5.2.2.

Testbench Components

5.2.2.1.

5.2.2.2.

5.2.2.3.

5.2.2.4.

5.2.3.

Stimulus Generation

5.2.3.1.

Directed Testing

5.2.3.2.

Constrained Random Testing

5.2.3.3.

5.2.4.

Clock and Reset Generation

5.2.4.1.

Clock Generation Techniques

5.2.4.2.

Reset Strategies

5.2.5.

Output Monitoring

5.2.5.1.

Response Checking

5.2.5.2.

Waveform Analysis

5.3.

Verification Techniques

5.3.1.

Black Box Testing

5.3.2.

White Box Testing

5.3.3.

Regression Testing

5.3.4.

Corner Case Testing

5.3.5.

5.4.

Self-Checking Testbenches

5.4.1.

5.4.1.1.

Immediate Assertions

5.4.1.2.

Concurrent Assertions

5.4.1.3.

Temporal Assertions

5.4.2.

Checking Output Against Expected Results

5.4.3.

Comparing Results Against a Golden Model

5.4.4.

File I/O for Test Vectors

5.4.4.1.

Reading Test Vectors from Files

5.4.4.2.

Writing Results to Files

5.4.5.

Automatic Result Verification

5.5.

Advanced Verification Concepts

5.5.1.

Coverage-Driven Verification

5.5.1.1.

Functional Coverage

5.5.1.2.

5.5.1.2.1.

Statement Coverage

5.5.1.2.2.

Branch Coverage

5.5.1.2.3.

Expression Coverage

5.5.1.2.4.

Toggle Coverage

5.5.2.

Constrained Random Verification

5.5.2.1.

Random Stimulus Generation

5.5.2.2.

Constraint Specification

5.5.3.

Assertion-Based Verification

5.5.3.1.

Property Specification

5.5.3.2.

5.6.

Simulation Tools and Techniques

5.6.1.

Simulation Environments

5.6.1.1.

Vendor Simulators

5.6.1.1.1.

Xilinx Vivado Simulator

5.6.1.1.2.

5.6.1.2.

Third-Party Simulators

5.6.1.2.1.

5.6.1.2.2.

Cadence Xcelium

5.6.2.

Waveform Viewers

5.6.2.1.

5.6.2.2.

Hierarchical Browsing

5.6.2.3.

Measurement Tools

5.6.3.

Debug Techniques

5.6.3.1.

5.6.3.2.

Single Stepping

5.6.3.3.

Variable Inspection

5.6.4.

Performance Optimization

5.6.4.1.

Simulation Speed Optimization

5.6.4.2.

Memory Usage Optimization

5.7.

Formal Verification

5.7.1.

Introduction to Formal Methods

5.7.2.

Property Checking

5.7.2.1.

Safety Properties

5.7.2.2.

Liveness Properties

5.7.3.

Equivalence Checking

5.7.3.1.

Combinational Equivalence

5.7.3.2.

Sequential Equivalence

5.7.4.

5.7.5.

Formal Verification Tools

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6. Timing Constraints and Analysis