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Computer Science
Software Engineering
FPGA Development
1. Introduction to FPGAs and Digital Logic
2. FPGA Architecture Fundamentals
3. Hardware Description Languages
4. The FPGA Design Flow
5. Simulation and Verification
6. Timing Constraints and Analysis
7. Advanced HDL Design Techniques
8. System-on-Chip FPGA Design
9. On-Chip Debugging and Practical Implementation
10. High-Level Synthesis
Simulation and Verification
The Importance of Verification
Detecting Design Errors
Ensuring Functional Correctness
Reducing Debug Time in Hardware
Cost of Late Bug Discovery
Verification Methodologies
Testbench Architecture
Unit Under Test Instantiation
Testbench Components
Driver
Monitor
Scoreboard
Checker
Stimulus Generation
Directed Testing
Constrained Random Testing
Input Vectors
Clock and Reset Generation
Clock Generation Techniques
Reset Strategies
Output Monitoring
Response Checking
Waveform Analysis
Verification Techniques
Black Box Testing
White Box Testing
Regression Testing
Corner Case Testing
Stress Testing
Self-Checking Testbenches
Assertions
Immediate Assertions
Concurrent Assertions
Temporal Assertions
Checking Output Against Expected Results
Comparing Results Against a Golden Model
File I/O for Test Vectors
Reading Test Vectors from Files
Writing Results to Files
Automatic Result Verification
Advanced Verification Concepts
Coverage-Driven Verification
Functional Coverage
Code Coverage
Statement Coverage
Branch Coverage
Expression Coverage
Toggle Coverage
Constrained Random Verification
Random Stimulus Generation
Constraint Specification
Assertion-Based Verification
Property Specification
Temporal Logic
Simulation Tools and Techniques
Simulation Environments
Vendor Simulators
Xilinx Vivado Simulator
Intel ModelSim
Third-Party Simulators
Synopsys VCS
Cadence Xcelium
Waveform Viewers
Signal Tracing
Hierarchical Browsing
Measurement Tools
Debug Techniques
Breakpoints
Single Stepping
Variable Inspection
Performance Optimization
Simulation Speed Optimization
Memory Usage Optimization
Formal Verification
Introduction to Formal Methods
Property Checking
Safety Properties
Liveness Properties
Equivalence Checking
Combinational Equivalence
Sequential Equivalence
Model Checking
Formal Verification Tools
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4. The FPGA Design Flow
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6. Timing Constraints and Analysis