FPGA Development

4.

The FPGA Design Flow

4.1.

Overview of the Toolchain

4.1.1.

Vendor Toolchains

4.1.1.1.

4.1.1.2.

Intel Quartus Prime

4.1.1.3.

Lattice Diamond

4.1.1.4.

Microsemi Libero

4.1.2.

Third-Party Tools

4.1.2.1.

Synopsys Design Compiler

4.1.2.2.

4.1.3.

Design Flow Stages

4.1.4.

Project Management

4.2.

4.2.1.

Writing HDL Code

4.2.1.1.

Text Editors and IDEs

4.2.1.2.

Syntax Highlighting

4.2.1.3.

4.2.2.

Schematic Capture

4.2.2.1.

Graphical Design Entry

4.2.2.2.

Symbol Libraries

4.2.3.

IP Integrator Tools

4.2.3.1.

Block Design Environment

4.2.3.2.

4.2.3.3.

Custom IP Creation

4.2.4.

Design Constraints Entry

4.2.4.1.

Timing Constraints

4.2.4.2.

Physical Constraints

4.2.4.3.

Design Rule Constraints

4.3.

Simulation and Functional Verification

4.3.1.

Purpose of Simulation

4.3.2.

Simulation Types

4.3.2.1.

Behavioral Simulation

4.3.2.2.

Post-Synthesis Simulation

4.3.2.3.

Post-Implementation Simulation

4.3.3.

Verifying Logic Before Synthesis

4.3.4.

Writing Testbenches

4.3.5.

Stimulus Generation

4.3.5.1.

Manual Test Vectors

4.3.5.2.

Automated Test Generation

4.3.6.

Analyzing Waveforms

4.3.7.

Debugging Simulation Results

4.3.8.

Coverage Analysis

4.4.

4.4.1.

HDL to Netlist Translation

4.4.2.

Logic Optimization

4.4.2.1.

Boolean Optimization

4.4.2.2.

Resource Sharing

4.4.2.3.

Constant Propagation

4.4.2.4.

Dead Code Elimination

4.4.3.

Technology Mapping

4.4.3.1.

4.4.3.2.

4.4.3.3.

4.4.4.

Resource Estimation

4.4.5.

Synthesis Reports

4.4.6.

Synthesis Constraints

4.5.

4.5.1.

4.5.1.1.

Assigning Logic to Physical Locations

4.5.1.2.

Placement Algorithms

4.5.1.3.

Placement Constraints

4.5.1.4.

4.5.2.

4.5.2.1.

Connecting Logic with Interconnects

4.5.2.2.

Routing Algorithms

4.5.2.3.

Routing Constraints

4.5.2.4.

Congestion Analysis

4.5.3.

4.5.3.1.

Timing-Driven Optimization

4.5.3.2.

Power Optimization

4.5.3.3.

Area Optimization

4.6.

Timing Analysis

4.6.1.

Static Timing Analysis

4.6.1.1.

Setup Time Analysis

4.6.1.2.

Hold Time Analysis

4.6.1.3.

Clock Skew Analysis

4.6.2.

4.6.2.1.

Worst Negative Slack

4.6.2.2.

Total Negative Slack

4.6.2.3.

Critical Path Reports

4.6.3.

Verifying Performance Against Constraints

4.6.4.

Identifying Timing Violations

4.6.5.

Timing Closure Techniques

4.7.

4.7.1.

Static Power Analysis

4.7.2.

Dynamic Power Analysis

4.7.3.

Power Optimization Techniques

4.7.4.

4.8.

Bitstream Generation

4.8.1.

Creating the Final Configuration File

4.8.2.

Bitstream Formats

4.8.3.

Compression Options

4.8.4.

Security and Encryption Options

4.8.4.1.

Bitstream Encryption

4.8.4.2.

4.8.5.

Partial Reconfiguration Bitstreams

4.9.

Hardware Programming and Debugging

4.9.1.

Programming Interfaces

4.9.1.1.

4.9.1.2.

4.9.1.3.

4.9.1.4.

4.9.2.

Loading the Bitstream onto the FPGA

4.9.3.

Configuration Modes

4.9.4.

In-System Debugging

4.9.4.1.

Logic Analyzers

4.9.4.2.

4.9.4.3.

4.9.5.

Hardware Validation

4.9.6.

Board-Level Testing

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5. Simulation and Verification