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Computer Science
Software Engineering
FPGA Development
1. Introduction to FPGAs and Digital Logic
2. FPGA Architecture Fundamentals
3. Hardware Description Languages
4. The FPGA Design Flow
5. Simulation and Verification
6. Timing Constraints and Analysis
7. Advanced HDL Design Techniques
8. System-on-Chip FPGA Design
9. On-Chip Debugging and Practical Implementation
10. High-Level Synthesis
Hardware Description Languages
Introduction to HDLs
Purpose of HDLs in Digital Design
Describing Hardware vs. Programming Software
Concurrency in Hardware
Simulation vs. Synthesis
Concept of Synthesis
Abstraction Levels
Behavioral Level
Register Transfer Level
Gate Level
Switch Level
Verilog
Language Fundamentals
Module Definition and Structure
Port Declarations
Input Ports
Output Ports
Inout Ports
Data Types
Net Types
wire
tri
supply0 and supply1
Variable Types
reg
integer
real
time
Vector Declarations
Arrays
Parameters and Local Parameters
Operators
Arithmetic Operators
Logical Operators
Bitwise Operators
Reduction Operators
Shift Operators
Relational Operators
Equality Operators
Conditional Operator
Concatenation Operator
Constants and Literals
Number Formats
String Literals
Modeling Styles
Structural Modeling
Gate-Level Primitives
Module Instantiation and Hierarchy
Port Mapping
Positional Association
Named Association
Dataflow Modeling
Continuous Assignments
Assign Statement Usage
Delay Modeling
Behavioral Modeling
Procedural Blocks
always Block
initial Block
Blocking vs. Non-Blocking Assignments
Sensitivity Lists
Event Control
Timing Control
Control Constructs
Conditional Statements
if-else Statements
Nested if Statements
Case Statements
case Statement
casex Statement
casez Statement
Loop Statements
for Loops
while Loops
repeat Loops
forever Loops
Generate Statements
Generate for Loops
Generate if Statements
Generate case Statements
Functions and Tasks
Function Declarations
Task Declarations
Automatic Functions and Tasks
Recursive Functions
Compiler Directives
Include Directive
Define Directive
Ifdef Conditional Compilation
Timescale Directive
System Tasks and Functions
Display Tasks
File I/O Tasks
Simulation Control Tasks
Random Number Functions
Testbench Construction in Verilog
Testbench Structure
Writing Stimulus
Clock Generation
Reset Generation
Monitoring Outputs
File-Based Testing
VHDL
Language Fundamentals
Design Units
Entity Declaration
Architecture Body
Configuration Declaration
Package Declaration
Package Body
Port Declarations
Port Modes
in
out
inout
buffer
Data Types
Scalar Types
std_logic
bit
boolean
integer
real
character
Composite Types
std_logic_vector
bit_vector
string
Arrays
Records
Subtypes
User-Defined Types
Enumerated Types
Objects
Constants
Variables
Signals
Files
Operators
Arithmetic Operators
Logical Operators
Relational Operators
Shift and Rotate Operators
Concatenation Operator
Concurrent Statements
Signal Assignments
Simple Signal Assignment
Conditional Signal Assignment
Selected Signal Assignment
Component Instantiation
Component Declaration
Component Instantiation
Port Mapping
Positional Association
Named Association
Generate Statements
For Generate
If Generate
Block Statements
Sequential Statements
Process Statements
Process Declaration
Sensitivity Lists
Wait Statements
Sequential Signal Assignment
Variable Assignment
Control Statements
if-then-else Statements
case Statements
Loop Statements
for Loops
while Loops
loop Statements
next and exit Statements
Procedure Calls
Assertion Statements
Subprograms
Functions
Function Declaration
Function Body
Pure and Impure Functions
Procedures
Procedure Declaration
Procedure Body
Libraries and Packages
Library Declarations
Use Clauses
Standard Libraries
STD Library
IEEE Library
IEEE Packages
std_logic_1164 Package
numeric_std Package
numeric_bit Package
std_logic_arith Package
std_logic_unsigned Package
Attributes
Predefined Attributes
Array Attributes
Type Attributes
Signal Attributes
User-Defined Attributes
Testbench Construction in VHDL
Testbench Architecture
Writing Stimulus
Clock and Reset Generation
Monitoring Outputs
File I/O Operations
Assert Statements for Verification
SystemVerilog
Enhancements over Verilog
Data Types and Structures
Interfaces
Classes and Object-Oriented Programming
Assertions
Coverage
Constrained Random Verification
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2. FPGA Architecture Fundamentals
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4. The FPGA Design Flow