PCI and Device Management

4.

Evolution to PCI Express (PCIe)

4.1.

Limitations of Parallel PCI

4.1.1.

Bandwidth Sharing Constraints

4.1.1.1.

Shared Bus Bandwidth Limitations

4.1.1.2.

Device Contention Issues

4.1.2.

Electrical and Physical Constraints

4.1.2.1.

Clock Skew Problems

4.1.2.2.

Signal Integrity Issues

4.1.2.3.

Limited Pin Count

4.1.2.4.

Connector Size Limitations

4.1.3.

Scalability Issues

4.1.3.1.

Maximum Device Limitations

4.1.3.2.

Bus Length Restrictions

4.1.3.3.

Performance Bottlenecks

4.1.4.

Power Consumption Concerns

4.2.

Introduction to PCIe Architecture

4.2.1.

Shift from Parallel to Serial Communication

4.2.1.1.

Serial Data Transmission Benefits

4.2.1.2.

Differential Signaling Advantages

4.2.1.3.

Reduced Pin Count Requirements

4.2.2.

Point-to-Point Topology

4.2.2.1.

Direct Device Connections

4.2.2.2.

Elimination of Bus Contention

4.2.2.3.

Dedicated Bandwidth per Device

4.2.3.

Lane and Link Concepts

4.2.3.1.

Lane Structure and Organization

4.2.3.2.

Link Width Configurations

4.2.3.2.1.

4.2.3.2.2.

4.2.3.2.3.

4.2.3.2.4.

4.2.3.2.5.

4.2.3.3.

Bandwidth Scaling Mechanisms

4.2.3.4.

Lane Aggregation

4.3.

PCIe Protocol Architecture

4.3.1.

Layered Protocol Design

4.3.1.1.

Transaction Layer

4.3.1.1.1.

Packet-Based Communication

4.3.1.1.2.

Transaction Types

4.3.1.1.2.1.

Memory Transactions

4.3.1.1.2.2.

I/O Transactions

4.3.1.1.2.3.

Configuration Transactions

4.3.1.1.2.4.

Message Transactions

4.3.1.1.3.

Transaction Layer Packets (TLPs)

4.3.1.1.4.

Flow Control Mechanisms

4.3.1.2.

Data Link Layer

4.3.1.2.1.

Error Detection Mechanisms

4.3.1.2.2.

Error Correction Mechanisms

4.3.1.2.3.

Acknowledgment Protocols

4.3.1.2.4.

Flow Control Credits

4.3.1.2.5.

Retry Mechanisms

4.3.1.3.

4.3.1.3.1.

Electrical Specifications

4.3.1.3.2.

Signaling Specifications

4.3.1.3.3.

Connector Types and Pinouts

4.3.1.3.4.

Lane Initialization

4.3.1.3.5.

Link Training Sequences

4.3.2.

PCIe Hierarchy and Topology

4.3.2.1.

4.3.2.1.1.

Connection to CPU

4.3.2.1.2.

Connection to System Memory

4.3.2.1.3.

Root Port Functions

4.3.2.2.

4.3.2.2.1.

Multi-Port Device Interconnection

4.3.2.2.2.

Upstream and Downstream Ports

4.3.2.2.3.

Packet Routing Functions

4.3.2.3.

4.3.2.3.1.

Device Attachment Methods

4.3.2.3.2.

Endpoint Configuration

4.4.

PCIe Generations and Evolution

4.4.1.

4.4.1.1.

Data Rates and Bandwidth

4.4.1.2.

Initial Feature Set

4.4.2.

4.4.2.1.

Performance Improvements

4.4.2.2.

4.4.3.

4.4.3.1.

Enhanced Performance

4.4.3.2.

Advanced Features

4.4.4.

PCIe 4.0 and Beyond

4.4.4.1.

Latest Developments

4.4.4.2.

4.5.

Software Compatibility and Configuration

4.5.1.

Backwards Compatibility with PCI Software Model

4.5.1.1.

Legacy Software Support

4.5.1.2.

Configuration Space Compatibility

4.5.2.

Extended Configuration Space (ECAM)

4.5.2.1.

Enhanced Configuration Access

4.5.2.2.

4KB Configuration Space per Device

4.5.2.3.

Memory-Mapped Configuration Access

4.5.3.

Bus, Device, Function (BDF) Model Preservation

4.5.3.1.

Addressing Consistency

4.5.3.2.

Software Compatibility Benefits

4.6.

Advanced PCIe Features

4.6.1.

Enhanced Interrupt Handling

4.6.1.1.

Legacy INTx Emulation

4.6.1.1.1.

Compatibility Mechanisms

4.6.1.1.2.

Virtual Wire Signaling

4.6.1.2.

Message Signaled Interrupts (MSI)

4.6.1.2.1.

MSI Mechanism and Operation

4.6.1.2.2.

Advantages Over Legacy Interrupts

4.6.1.2.3.

MSI Configuration

4.6.1.3.

Extended Message Signaled Interrupts (MSI-X)

4.6.1.3.1.

Multiple Interrupt Vector Support

4.6.1.3.2.

Independent Interrupt Masking

4.6.1.3.3.

MSI-X Table Structure

4.6.2.

Advanced Power Management

4.6.2.1.

Active State Power Management (ASPM)

4.6.2.1.1.

Power State Definitions

4.6.2.1.2.

State Transition Mechanisms

4.6.2.2.

Link Power States

4.6.2.2.1.

L0 (Active State)

4.6.2.2.2.

L0s (Standby State)

4.6.2.2.3.

L1 (Low Power Standby)

4.6.2.2.4.

L2 (Auxiliary Power)

4.6.2.2.5.

4.6.2.3.

Device Power Management

4.6.2.3.1.

D0 through D3 States

4.6.2.3.2.

Wake-Up Mechanisms

4.6.3.

Hot-Plug and Hot-Swap Support

4.6.3.1.

Hardware Requirements

4.6.3.2.

Software Support Mechanisms

4.6.3.3.

Hot-Plug Controllers

4.6.3.4.

Attention Button Support

4.6.3.5.

Power Controller Integration

4.6.3.6.

Use Cases and Applications

4.6.3.7.

Safety Considerations and Limitations

4.6.4.

Quality of Service (QoS) Features

4.6.4.1.

Traffic Classes

4.6.4.2.

Virtual Channels

4.6.4.3.

Bandwidth Allocation

4.6.5.

Advanced Error Reporting (AER)

4.6.5.1.

Error Detection Mechanisms

4.6.5.2.

Error Reporting Protocols

4.6.5.3.

Error Recovery Procedures

4.6.6.

Single Root I/O Virtualization (SR-IOV)

4.6.6.1.

Virtualization Support

4.6.6.2.

Physical and Virtual Functions

4.6.6.3.

Resource Sharing Mechanisms

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3. The Device Management Lifecycle

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1. Fundamentals of Peripheral Interconnects