PCI and Device Management

  1. PCI Architecture and Hardware
    1. The Logical Hierarchy
      1. Host Bridge (Root Complex)
        1. Role in System Architecture
          1. Connection to CPU
            1. Connection to System Memory
              1. Address Translation Functions
              2. PCI Bus Segments
                1. Definition of a Bus Segment
                  1. Segment Numbering Scheme
                    1. Maximum Devices per Segment
                    2. PCI-to-PCI Bridges
                      1. Purpose and Function
                        1. Primary Bus Numbers
                          1. Secondary Bus Numbers
                            1. Bridge Configuration Requirements
                              1. Subordinate Bus Numbers
                              2. PCI Endpoint Devices
                                1. Types of Endpoint Devices
                                  1. Device Attachment to the Bus
                                    1. Single-Function Devices
                                      1. Multi-Function Devices
                                    2. Device Identification and Addressing
                                      1. Bus, Device, Function (BDF) Addressing
                                        1. Bus Number
                                          1. Range and Assignment
                                            1. Hierarchical Bus Structure
                                            2. Device Number
                                              1. Device Slot Identification
                                                1. Physical vs. Logical Device Numbers
                                                2. Function Number
                                                  1. Single-Function Devices
                                                    1. Multi-Function Devices
                                                      1. Function Enumeration
                                                    2. Device Identification Fields
                                                      1. Vendor ID
                                                        1. Device ID
                                                          1. Subsystem Vendor ID
                                                            1. Subsystem ID
                                                          2. The PCI Configuration Space
                                                            1. Purpose and Importance
                                                              1. Device Discovery Process
                                                                1. Resource Assignment Mechanism
                                                                  1. Device Configuration Management
                                                                  2. Accessing the Configuration Space
                                                                    1. I/O Port Mechanism
                                                                      1. CONFIG_ADDRESS Register
                                                                        1. CONFIG_DATA Register
                                                                          1. Addressing Scheme
                                                                            1. Read Operations
                                                                              1. Write Operations
                                                                              2. Memory-Mapped Access
                                                                                1. Enhanced Configuration Access Mechanism (ECAM)
                                                                                  1. Memory-Mapped Configuration Space
                                                                                2. Configuration Space Header Structure
                                                                                  1. Common Header Fields
                                                                                    1. Vendor ID Field
                                                                                      1. Device ID Field
                                                                                        1. Command Register
                                                                                          1. Status Register
                                                                                            1. Revision ID Field
                                                                                              1. Class Code Field
                                                                                                1. Subclass Code Field
                                                                                                  1. Programming Interface Field
                                                                                                    1. Cache Line Size
                                                                                                      1. Latency Timer
                                                                                                        1. Header Type Field
                                                                                                          1. BIST (Built-In Self Test) Field
                                                                                                          2. Type 0 Header (Endpoint Devices)
                                                                                                            1. Layout and Organization
                                                                                                              1. Device-Specific Fields
                                                                                                                1. Base Address Registers
                                                                                                                  1. Cardbus CIS Pointer
                                                                                                                    1. Subsystem Vendor ID
                                                                                                                      1. Subsystem ID
                                                                                                                        1. Expansion ROM Base Address
                                                                                                                          1. Capabilities Pointer
                                                                                                                            1. Interrupt Pin
                                                                                                                              1. Interrupt Line
                                                                                                                                1. Min_Gnt and Max_Lat
                                                                                                                                2. Type 1 Header (PCI-to-PCI Bridges)
                                                                                                                                  1. Bridge-Specific Fields
                                                                                                                                    1. Primary Bus Number
                                                                                                                                      1. Secondary Bus Number
                                                                                                                                        1. Subordinate Bus Number
                                                                                                                                          1. Secondary Latency Timer
                                                                                                                                            1. I/O Base and Limit
                                                                                                                                              1. Memory Base and Limit
                                                                                                                                                1. Prefetchable Memory Base and Limit
                                                                                                                                                  1. Bridge Control Register
                                                                                                                                              2. Resource Allocation and Management
                                                                                                                                                1. Base Address Registers (BARs)
                                                                                                                                                  1. Purpose of BARs
                                                                                                                                                    1. Number and Types of BARs
                                                                                                                                                      1. BAR Encoding Schemes
                                                                                                                                                        1. Memory Space Mapping (MMIO)
                                                                                                                                                          1. Memory Space Decoding
                                                                                                                                                            1. Prefetchable Memory
                                                                                                                                                              1. Non-Prefetchable Memory
                                                                                                                                                                1. 32-bit Memory Addressing
                                                                                                                                                                  1. 64-bit Memory Addressing
                                                                                                                                                                  2. I/O Space Mapping
                                                                                                                                                                    1. I/O Space Decoding
                                                                                                                                                                      1. I/O Address Ranges
                                                                                                                                                                      2. Determining Resource Size Requirements
                                                                                                                                                                        1. BAR Sizing Algorithm
                                                                                                                                                                          1. Resource Size Calculation
                                                                                                                                                                        2. Interrupt Management
                                                                                                                                                                          1. Interrupt Pin Assignment
                                                                                                                                                                            1. INTA# Pin
                                                                                                                                                                              1. INTB# Pin
                                                                                                                                                                                1. INTC# Pin
                                                                                                                                                                                  1. INTD# Pin
                                                                                                                                                                                    1. Pin Routing and Swizzling
                                                                                                                                                                                    2. Interrupt Line Configuration
                                                                                                                                                                                      1. Mapping to System IRQs
                                                                                                                                                                                        1. Software Configuration
                                                                                                                                                                                          1. Interrupt Sharing Mechanisms
                                                                                                                                                                                        2. Expansion ROM Support
                                                                                                                                                                                          1. ROM Base Address Register
                                                                                                                                                                                            1. ROM Image Structure
                                                                                                                                                                                              1. ROM Shadowing

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                                                                                                                                                                                          1. Fundamentals of Peripheral Interconnects

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                                                                                                                                                                                          3. The Device Management Lifecycle