Microelectronic Circuits

6.

Analog Integrated Circuit Design

6.1.

Single-Stage Amplifiers

6.1.1.

Active Load Concepts

6.1.1.1.

Current Source Loads

6.1.1.2.

Advantages over Resistive Loads

6.1.1.3.

Implementation Techniques

6.1.2.

Common-Source with Active Load

6.1.2.1.

Circuit Configuration

6.1.2.2.

Gain Enhancement

6.1.2.3.

6.1.3.

Source Follower Applications

6.1.3.1.

Buffer Amplifiers

6.1.3.2.

6.1.4.

Common-Gate Applications

6.1.4.1.

Current Buffers

6.1.4.2.

Cascode Configurations

6.2.

Differential Amplifiers

6.2.1.

Differential Pair Fundamentals

6.2.1.1.

Balanced Operation

6.2.1.2.

Common-Mode Rejection

6.2.1.3.

Input Offset Effects

6.2.2.

MOS Differential Pair

6.2.2.1.

Large-Signal Analysis

6.2.2.2.

Small-Signal Analysis

6.2.2.3.

Current Mirror Loads

6.2.3.

BJT Differential Pair

6.2.3.1.

Emitter-Coupled Pair

6.2.3.2.

Tail Current Source

6.2.3.3.

Temperature Effects

6.2.4.

Differential Amplifier Specifications

6.2.4.1.

Differential Gain

6.2.4.2.

Common-Mode Gain

6.2.4.3.

Common-Mode Rejection Ratio

6.2.4.4.

Input Offset Voltage

6.2.4.5.

Input Bias Current

6.3.

Multistage Amplifier Design

6.3.1.

Cascade Amplifier Configurations

6.3.1.1.

Gain Distribution

6.3.1.2.

Bandwidth Considerations

6.3.1.3.

Interstage Coupling

6.3.2.

Cascode Amplifier Configurations

6.3.2.1.

Current Gain Enhancement

6.3.2.2.

Bandwidth Extension

6.3.2.3.

Miller Effect Reduction

6.3.3.

Darlington and Compound Configurations

6.3.3.1.

Current Gain Multiplication

6.3.3.2.

Input Impedance Enhancement

6.4.

Frequency Response Analysis

6.4.1.

Low-Frequency Response

6.4.1.1.

Coupling Capacitor Effects

6.4.1.2.

Bypass Capacitor Effects

6.4.1.3.

Low-Frequency Poles

6.4.2.

High-Frequency Response

6.4.2.1.

Device Capacitances

6.4.2.2.

6.4.2.3.

High-Frequency Poles

6.4.3.

Frequency Response of Amplifier Stages

6.4.3.1.

Single-Pole Response

6.4.3.2.

Multi-Pole Response

6.4.3.3.

Dominant Pole Approximation

6.4.4.

Bandwidth Enhancement Techniques

6.4.4.1.

Cascode Configurations

6.4.4.2.

6.4.4.3.

Peaking Techniques

6.5.

Feedback in Amplifiers

6.5.1.

Feedback Theory

6.5.1.1.

Feedback Topology

6.5.1.2.

6.5.1.3.

6.5.2.

Negative Feedback Benefits

6.5.2.1.

Gain Stabilization

6.5.2.2.

Bandwidth Extension

6.5.2.3.

Distortion Reduction

6.5.2.4.

Input/Output Impedance Control

6.5.3.

Feedback Topologies

6.5.3.1.

Voltage-Series Feedback

6.5.3.2.

Voltage-Shunt Feedback

6.5.3.3.

Current-Series Feedback

6.5.3.4.

Current-Shunt Feedback

6.5.4.

Stability Analysis

6.5.4.1.

Nyquist Criterion

6.5.4.2.

Bode Plot Analysis

6.5.4.3.

6.5.4.4.

6.5.4.5.

Compensation Techniques

6.6.

Power Amplifiers and Output Stages

6.6.1.

Power Amplifier Classes

6.6.1.1.

Class A Operation

6.6.1.2.

Class B Operation

6.6.1.3.

Class AB Operation

6.6.1.4.

Class C Operation

6.6.2.

Push-Pull Output Stages

6.6.2.1.

Complementary Symmetry

6.6.2.2.

Quasi-Complementary

6.6.2.3.

Crossover Distortion

6.6.3.

Power Efficiency Analysis

6.6.3.1.

Efficiency Calculations

6.6.3.2.

Power Dissipation

6.6.3.3.

Thermal Considerations

6.6.4.

Protection Circuits

6.6.4.1.

Current Limiting

6.6.4.2.

Thermal Protection

6.6.4.3.

Safe Operating Area

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7. Active Filters and Signal Processing