Category: Transactional memory

IBM Z is a family name used by IBM for all of its z/Architecture mainframe computers.In July 2017, with another generation of products, the official family was changed to IBM Z from IBM z Systems; the
POWER8 is a family of superscalar multi-core microprocessors based on the Power ISA, announced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER F
The IBM A2 is an open source massively multicore capable and multithreaded 64-bit Power ISA processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the
Kaby Lake
Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing p
Cannon Lake (microprocessor)
Cannon Lake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture. As a die shrink, Cannon Lake is a new process in Intel's process-architecture-opt
Tiger Lake
Tiger Lake is Intel's codename for the 11th generation Intel Core mobile processors based on the new Willow Cove Core microarchitecture, manufactured using Intel's third-generation 10 nm process node
Transactional memory
In computer science and engineering, transactional memory attempts to simplify concurrent programming by allowing a group of load and store instructions to execute in an atomic way. It is a concurrenc
IBM zEC12 (microprocessor)
The zEC12 microprocessor (zEnterprise EC12 or just z12) is a chip made by IBM for their zEnterprise EC12 and zEnterprise BC12 mainframe computers, announced on August 28, 2012. It is manufactured at t
Software transactional memory
In computer science, software transactional memory (STM) is a concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing. It is an
IBM Blue Gene
Blue Gene is an IBM project aimed at designing supercomputers that can reach operating speeds in the petaFLOPS (PFLOPS) range, with low power consumption. The project created three generations of supe
POWER9 is a family of superscalar, multithreading, multi-core microprocessors produced by IBM, based on the Power ISA. It was announced in August 2016. The POWER9-based processors are being manufactur
In computer science, load-linked/store-conditional (LL/SC), sometimes known as load-reserved/store-conditional (LR/SC), are a pair of instructions used in multithreading to achieve synchronization. Lo
Rock (processor)
Rock (or ROCK) was a multithreading, multicore, SPARC microprocessor under development at Sun Microsystems. Canceled in 2010, it was a separate project from the SPARC T-Series (CoolThreads/Niagara) fa
Haswell (microarchitecture)
Haswell is the codename for a processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge (which is a die shrink/tick of the Sandy Bridge microarchitectu
Coffee Lake
Coffee Lake is Intel's codename for its eighth generation Core microprocessor family, announced on September 25, 2017. It is manufactured using Intel's second 14 nm process node refinement. Desktop Co
Broadwell (microarchitecture)
Broadwell is the fifth generation of the Intel Core processors. It is Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle a
Ice Lake (microprocessor)
Ice Lake is Intel's codename for the 10th generation Intel Core mobile and 3rd generation Xeon Scalable server processors based on the Sunny Cove microarchitecture. Ice Lake represents an Architecture
Skylake (microarchitecture)
Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the s
Transactional Synchronization Extensions
Transactional Synchronization Extensions (TSX), also called Transactional Synchronization Extensions New Instructions (TSX-NI), is an extension to the x86 instruction set architecture (ISA) that adds
Cooper Lake (microprocessor)
Cooper Lake is Intel's codename for the third-generation of their Xeon scalable processors, developed as the successor to Cascade Lake. Cooper Lake processors are targeted at the 4S and 8S segments of
Blue Gene/Q
No description available.
Advanced Synchronization Facility
Advanced Synchronization Facility (ASF) is a proposed extension to the x86-64 instruction set architecture that adds hardware transactional memory support. It was introduced by AMD; the latest specifi
Cascade Lake (microprocessor)
Cascade Lake is an Intel codename for a server, workstation and enthusiast computing processor microarchitecture, launched in April 2019. In Intel's process-architecture-optimization model, which used